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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
FEATURES
* 1 differential 3.3V LVPECL output * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal * Output frequency: 125MHz, using a 25MHz crystal * VCO range: 490MHz - 640MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.41ps (typical) (for 3.3V) * Full 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS843021I-01 is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS843021I-01 uses a 25MHz crystal to synthesize 125MHz. The ICS843021I-01 has excellent phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS843021I-01 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
BLOCK DIAGRAM
OE 25MHz XTAL_IN
PIN ASSIGNMENT
VCC XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 Q0 nQ0 VCC OE
OSC
XTAL_OUT
Phase Detector
VCO
/4 (fixed)
Q0 nQ0
ICS843021I-01
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
/20 (fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843021AGI-01 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 30, 2004
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
Type Description Core supply pin. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. Active high output enable. When logic HIGH, the outputs are enabled and active. When logic LOW, the outputs are disabled and are in a high impedance state. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 6 2, 3 4 5 7, 8 Name VCC XTAL_OUT, XTAL_IN V EE OE nQ0, Q0 Power Input Power Input Output Pullup
Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF K
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5V 50mA 100mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA= -40C TO 85C
Symbol VCC VCCA I EE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 60 Maximum 3.465 3.465 Units V V mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V5%, TA= -40C TO 85C
Symbol VCC VCCA I EE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 57 Maximum 2.625 2.625 Units V V mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA= -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE OE VCC = VIN = 3.465V or 2.5V VCC = 3.465V or 2.5V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 5 Units V V A A
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA= -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
843021AGI-01
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
Test Conditions Minimum Typical Fundamental 25 50 7 MHz pF Maximum Units
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance
TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V5%, TA= -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions Intergration Range: 1.875MHz - 20MHz 20% to 80% Minimum Typical 125 0.41 400 50 Maximum Units MHz ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot following this section.
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V5%, TA= -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions Intergration Range: 1.875MHz - 20MHz 20% to 80% Minimum Typical 125 0.42 400 50 Maximum Units MHz ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot following this section.
843021AGI-01
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 125MHZ (3.3V OR 2.5V)
0 -10 -20 -30 -40 -50
Gigabit Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz (3.3V) = 0.41ps (typical) 1.875MHz to 20MHz (2.5V) = 0.42ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k
Raw Phase Noise Data
Phase Noise Result by adding Gigabit Ethernet Filter to raw data
1M 10M 100M
OFFSET FREQUENCY (HZ)
843021AGI-01
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
2V
VCC
Qx
SCOPE
V CC
Qx
SCOPE
LVPECL
nQx
LVPECL
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
80%
Phase Noise Mask
80% VSW I N G
Clock Outputs
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQ0 Q0
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843021AGI-01
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
The ICS843021I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p
Figure 1. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
125
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
FIGURE 2A. LVPECL OUTPUT TERMINATION
843021AGI-01
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. A NOVEMBER 30, 2004
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
VCC=2.5V
2.5V
VCC=2.5V
R1 250
Zo = 50 Ohm
R3 250
Zo = 50 Ohm
+
+
Zo = 50 Ohm
2,5V LVPECL Driv er
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
R2 62.5
R4 62.5
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
843021AGI-01
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
two termination examples are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note.
APPLICATION SCHEMATIC
Figure 4 shows an example of ICS843021I-01 application schematic. In this example, the device is operated at VCC = 3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 25MHz quartz crystal. For the LVPECL output drivers, only
VCC = 3.3V 3.3V
C2 27pF X1 25MHz 18pF
U1 Zo = 50 Ohm 1 2 3 4 VCC XTAL_OUT XTAL_IN VEE 843021I-01 Q0 nQO Vcc OE 8 7 6 5
R3 133
R5 133
+ OE Zo = 50 Ohm -
C1 27pF
R4 82.5
R6 82.5
VCC
C3 10uF
C4 .1uF
C5 .1uF
Zo = 50
+
Zo = 50
-
R2 50
R1 50
R3 50
Optional Termination
FIGURE 4. ICS843021I-01 SCHEMATIC EXAMPLE
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843021I-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843021I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 60mA = 207.9mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 207.9mW + 30mW = 237.9mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.238W * 90.5C/W = 106.5C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
843021AGI-01
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS843021I-01 is: 1765
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
8 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843021I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
Marking 1AI01 1AI01 Package 8 lead TSSOP 8 lead TSSOP on Tape and Reel Count 100 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843021AGI-01 ICS843021AGI-01T
The aforementioned trademarks, HiPerClockSTM
and FemtoClocksTM
are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843021AGI-01
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